Library prosa.analysis.facts.tdma
Require Export prosa.model.schedule.tdma.
Require Import prosa.util.all.
From mathcomp Require Import div.
Require Import prosa.util.all.
From mathcomp Require Import div.
In this section, we define the properties of TDMA and prove some basic lemmas.
Consider any task set ts...
... with a TDMA policy
Consider any task in ts
Assume task_time_slot is valid time slot
Obviously, the TDMA cycle is greater or equal than any task time slot which is
in TDMA cycle
Thus, a TDMA cycle is always positive
Slot offset is less then cycle
For a task, the sum of its slot offset and its time slot is
less then or equal to cycle.
Lemma Offset_add_slot_leq_cycle:
task_slot_offset ts task + task_time_slot task ≤ TDMA_cycle ts.
End TimeSlotFacts.
task_slot_offset ts task + task_time_slot task ≤ TDMA_cycle ts.
End TimeSlotFacts.
Now we prove that no two tasks share the same time slot at any time.
Consider any task in ts
Assume task_time_slot is valid time slot
Assume that slot order is total...
Hypothesis slot_order_total:
total_slot_order ts.
(*..., antisymmetric... *)
Hypothesis slot_order_antisymmetric:
antisymmetric_slot_order ts.
(*... and transitive. *)
Hypothesis slot_order_transitive:
transitive_slot_order.
total_slot_order ts.
(*..., antisymmetric... *)
Hypothesis slot_order_antisymmetric:
antisymmetric_slot_order ts.
(*... and transitive. *)
Hypothesis slot_order_transitive:
transitive_slot_order.
Then, we can prove that the difference value between two offsets is
at least a slot
Lemma relation_offset:
∀ tsk1 tsk2, tsk1 \in ts →
tsk2 \in ts →
slot_order tsk1 tsk2 →
tsk1 != tsk2 →
task_slot_offset ts tsk2 ≥
task_slot_offset ts tsk1 + task_time_slot tsk1 .
∀ tsk1 tsk2, tsk1 \in ts →
tsk2 \in ts →
slot_order tsk1 tsk2 →
tsk1 != tsk2 →
task_slot_offset ts tsk2 ≥
task_slot_offset ts tsk1 + task_time_slot tsk1 .
Then, we proved that no two tasks share the same time slot at any time.